Minima Processor


Dynamic Margining for
SoC Energy Optimization

Embedded devices must continuously incorporate more and more features without sacrificing energy efficiency. For example, in the fast-growing Hearables and True Wireless markets, System-on-Chips (SoC) must incorporate the latest voice-activity-detection and keyword recognition algorithms while providing battery life for all-day operation. Minima’s Dynamic Margining product enables an order of magnitude energy efficiency improvement in such SoC designs without compromising time to market.

Minima uses an IP delivery model that adds both hardware and software to CPU and DSP processors. What makes the Minima approach different is dynamic margining. Dynamic Margining enables the SoC to scale down to near-threshold voltage operation – key in achieving up to an order of magnitude energy savings – while adapting to its current environment.  Minima’s approach is backed up with real silicon results from customers’ SoCs. Minima’s technology is uniquely transferrable – it can be applied on any process node and any type of digital logic content, including MCUs, DSPs, NPUs and custom logic.

The challenge in ultra-wide operating voltages stems from semiconductor device physics and manufacturing: performance variance increases drastically as the operating voltage is lowered. Without Minima Dynamic Margining, all this variance must be built into the product tolerances, or margins, which would effectively consume all the potential energy-efficiency gains. That’s why so few systems have been able to reap the benefits of near-threshold voltage operation and where the name of Minima Processor’s unique solution, Dynamic Margining, originates from. It is based on more than a decade of research by Minima’s CTO & co-founder Lauri Koskinen’s team at Aalto and Turku Universities and VTT. The Minima team has been strengthened by semiconductor industry veterans and has secured several patents.

Minima Dynamic Margining Solution Achieves the Energy Optimum across Use Cases
• Run each use case / SW task at optimum operating point (Voltage & Frequency)

• Seamless, real-time switch between operating points (Ultra-Wide Frequency Scaling)
• Minimum energy operation for each operating point across PVT variance (Process, Voltage, Temperature)
• Ultra-wide voltage scaling down to near/sub-threshold voltages

Minima Vertical (HW + SW) IP Solution for System-on-Chip Semiconductors
• In-situ monitoring and control IP
• UW-DVFS Task/Driver for SW interface, OS integration example
• Optimization, customer application analysis and system optimization
• Implementation, monitor placement, design optimization

E/op (normalized)

Vdd (mv)

Minimum Energy Point (EOP)